The present invention relates to the formation of a hybrid SRAM cell on an SOI substrate and, more particularly, relates to an SRAM cell with both FinFET and planar transistors formed in the SOI layer of the SOI substrate.
A typical SRAM (static random access memory) cell typically includes pull-up, pull-down and pass-gate transistors (semiconductor devices). SRAM cells may require transistors with different width for best performance. Usually pull-down devices are wider than pull-up and pass-gate devices which complicates the lithography.
FIG. 1 illustrates a conventional SRAM cell 100 which includes a plurality of active areas 102, 104, 106, 108, 110, 112 and a plurality of gate electrodes 114, 116, 118, 120. The area 122 between the active areas 102, 104, 106, 108, 110, 112 is insulator, usually oxide. Where gate electrodes 114, 118 intersect with active areas 102, 110 are formed pull-down transistors 124, 126. Where gate electrodes 114, 116, 118, 120 intersect with active areas 104, 106, 108, 112 are formed pull-up or pass-gate transistors 128, 130, 132, 134 as shown in FIG. 1. The pull-down transistors 124, 126 have an active area 102, 110 with a width larger than active areas 104, 106, 108, 112 for optimum cell performance.